1. Field of the Invention
The present invention relates to an LSI containing an impedance trimming circuit to execute impedance matching on output impedance, input impedance, terminal resistance, or the like to suppress reflection of signals, thus allowing high-speed serial signals of high quality to be transferred, and in particular, to a trimming circuit for accurate and automatic adjustment.
2. Description of the Related Art
For a high-speed interface such as a USB2.0 (480 Mbps) or an LUDS (several Gbps), it has hitherto been essential to match input impedance, drive impedance, pull-up/pull-down resistance, or the like with a corresponding standard value (for example, xc2x110%) in order to suppress reflection of the waveform of a transferred signal, thus allowing a high-speed signal of high quality to be transmitted.
However, resistance elements manufactured using an LSI manufacturing process vary markedly (for example, xc2x120%). Further, the on resistance of an output transistor depends significantly on a temperature, a power voltage, or a threshold (for example, worst best=double/half). Accordingly, a certain adjustment circuit is required.
A first example of the prior art is Non-patent Document 1 (ESSCIRC2001 xe2x80x9cA New Impedance Control Circuit for USB2.0 Transceiverxe2x80x9d Koo K.-H. SAMSUNG Electronics.
In Non-patent Document 1, as shown in FIGS. 1 and 2, an operational amplifier adjusts a voltage drop at an external resistor Rext to an internal reference voltage Vref. An output signal from the operational amplifier is supplied to gates of two P channel MOS transistors. An output signal from an output buffer appears as a positive and negative differential outputs at a Data+terminal and a Dataxe2x88x92terminal, respectively, on the basis of voltage drops at internal resistors. This circuit has an auxiliary circuit for adjustment in addition to a circuit for data transfer. The auxiliary circuit finds, in a controlled manner, a code that adjusts the potential at a VA terminal to a value Vref.
In this case, output impedance is based on the internal resistor and MOS resistor. However, in this conventional example, this value is adjusted to 45 xcexa9xc2x15 xcexa9. Specifically, a comparator and a control circuit are used to adjust the sizes of the MOS transistors to find a code that results in the smallest error. Then, the sizes of the MOS transistors are increased or reduced, and this code is provided to the output buffer.
However, with this method, the circuit is affected by various variation factors such as a variation in reference voltage, an input offset voltage at the operational amplifier, a variation in the current ratio of a current source composed of the P channel MOS transistors, and a variation in MOS resistance. Thus, actually, it is difficult to accurately adjust the output impedance.
For example, if the current ratio of the current source composed of the P channel MOS transistors varies by about 5%, this mere variation causes the output impedance to reach the limit of the allowable variation range of 45 xcexa9xc2x15 xcexa9. Thus, disadvantageously, yield decreases and much labor is required to manage manufacturing steps. Therefore, in reality, it is difficult to accurately adjust the output impedance.
A second example of the prior art is Non-patent Document 2 (ESSCIR2001 xe2x80x9cDigitally tuneable on-chip line termination resistor for 2.5 Gbit/s LVDS receiver in 0.25 xcexcm standard CMOS technologyxe2x80x9d M. Kumric, F. Ebert, R. Rap, K. Welch Alcatel SEL Stuttgart (http://www. esscirc. org/esscirc2001/C01_Presentations/98 .pdf)).
In Non-patent Document 2, as shown in FIG. 3, a value for an internal trimming resistor is switched so that the externally provided reference voltage Vref is closest to a divided voltage resulting from an external resistor and the internal trimming resistor. Then, switching codes are used to switch input terminal resistance.
As shown in FIG. 4, the internal trimming resistor is composed of a resistor R0 connected directly between IP and IN and resistors R1 to R8 each connected via a switch turned on and off in a controlled manner using a code.
As shown in FIG. 5, in consideration of the range of a variation in the value for the internal resistor, a value for the resistor R0 is preset at a larger value. The resistors R1 to R8 are sequentially connected together to adjust the value for the internal trimming resistor over a wide range so that it falls within the range of a standard value of 100 xcexa9xc2x110 xcexa9.
However, this method requires an external circuit used to generate the reference voltage Vref as well as two external accurate resistors. This advantageously increases costs. Further, this method is used only for an input terminal section. The adjustment of the output impedance must include the adjustment of the on resistance of the output buffer as shown in the first example of the prior art.
A third example of the prior art is Patent Document 1.
In Patent Document 1 (Jpn. Pat. Appln. KOKAI Publication No. 2001-94048), as shown in FIG. 6, the operational amplifier is used to adjust a current from the current source composed of the P channel MOS transistors so that a voltage drop VZQ at an external resistor PQ is half the voltage at a power source VDDQ. Further, the size of an output driver is adjusted by using a current mirror to allow a current to flow through the output driver so that the resulting voltage drop equals the VZQ.
In this case, a variation in output resistance is affected directly by factors such as the offset voltage at the operational amplifier and a variation in current mirror current. Consequently, accurate adjustment of the current is limited.
It has thus been strongly desirable to provide an impedance trimming circuit which eliminates the adverse effects of variations associated with an LSI manufacturing process to accomplish accurate trimming and which can be constructed using a reduced number of external parts.
According to an aspect of the present invention, there is provided an impedance trimming circuit comprising a common bias section composed of a first series circuit having a first internal resistor and an external resistor connected in series via a first node and a first operational amplifier having a first input terminal connected to an internal reference voltage, a second input terminal connected to the first node, and an output terminal connected to the first series circuit; and an impedance trimming section composed of a second series circuit having a second internal resistor and an impedance dummy resistor connected in series via a second node, a comparator having a first input terminal connected to the first node and a second input terminal connected to the second node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which uses the plurality of switching codes to switch a resistance value of the impedance dummy resistor, wherein the first operational amplifier is also connected to the second series circuit, and an output signal from the code control circuit is input to a target impedance trimming resistor.